The present invention relates to semiconductor devices, and particularly relates to a MOS device including a gate insulating film made of a dielectric material having a high dielectric constant (hereinafter, referred to as a high-κ material) and a method for fabricating the device.
With recent increase in the integration degree and speed of semiconductor integrated circuit devices and expansion of the functionality thereof, the size of metal-oxide-semiconductor field effect transistors (MOSFETs) has been reduced. As the thickness of a gate insulating film decreases in accordance with this size reduction, the problem of increased gate leakage current caused by tunnel current comes to the surface. To solve this problem, there has been developed a technique with which a high-κ material of metal oxide such as hafnium oxide (HfO2) or zirconium oxide (ZrO2) is used for a gate insulating film so that the equivalent oxide thickness EOT is reduced with a physical thickness increased. The equivalent oxide thickness EOT is herein a thickness calculated from the thickness of a film made of a dielectric having a relative dielectric constant different from that of silicon oxide (SiO2) in terms of the relative dielectric constant of silicon oxide.
In the initial stage of development, the use of a gate insulating film made of metal oxide such as HfO2 or ZrO2 causes a problem in which an interface layer is formed between a silicon substrate and the gate insulating film. This interface layer has a low dielectric constant, so that the effective relative dielectric constant of the gate insulating film decreases, i.e., the equivalent oxide thickness EOT increases. Therefore, it was necessary to suppress formation of such an interface layer as much as possible. However, once the formation of an interface layer was successfully suppressed so that a high effective relative dielectric constant of the gate insulating film is maintained, i.e., the equivalent oxide thickness EOT is reduced afterward, there arises another problem in which carrier mobility deteriorates as compared to the case of a silicon oxide film and, consequently, desired operating current cannot be obtained. It has been considered that a cause of this problem is that (1) fixed charge included in a high-κ material electrically interferes with carriers in channel to cause the carrier mobility to deteriorate or (2) carriers in channel are scattered by a lattice in the high-κ material to cause the carrier mobility to deteriorate, for example. In non-patent literature 1 (M. Hiratani, S. Saito, Y. Shimamoto, and K. Torii, “Effective Electron Mobility Reduced by Remote Charge Scattering in High-κ Gate Stacks”, Jpn. J. Appl. Phys., Part 1 84, (2002) pp. 4521-4522), for example, a relationship between the mobility and the thickness of a silicon oxide film formed at the interface between a silicon substrate and a gate insulating film. According to this relationship, to avoid deterioration of the carrier mobility, channel (a substrate) and a high-κ material (a gate insulating film) are preferably separated from each other or a silicate structure in which a metal concentration in the entire high-κ material is reduced is preferably used. However, since the interface layer made of, for example, a silicon oxide film has a low relative dielectric constant, the effective relative dielectric constant of the gate insulating film extremely decreases, i.e., the equivalent oxide thickness EOT increases, in a case where the thickness of the interface layer is relatively large or in the case of a silicate structure in which the metal concentration is relatively low. Accordingly, each of a structure including an interface layer and a structure having a reduced metal concentration has a trade-off relationship with the case of not adopting these structures.
In addition, in recent yeas, there arises another problem in which the absolute value of the threshold voltage Vt during transistor operation increases due to reaction at the upper interface of the gate insulating film, i.e., reaction between materials for the gate insulating film and the gate electrode. Though a cause of this problem is unclear, it is reported that exposure of a substrate to a process at a high temperature of about 1000° C. in a transistor fabrication process such as activation performed on ions implanted in source/drain regions causes a gate-electrode material and an gate-insulating-film material to react with each other, so that an effective work function of the gate-electrode material varies. This phenomenon is called Fermi-level pinning. For example, in non-patent literature 2 (C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, “Fermi level pinning at the polySi/metal oxide interface”, Proceedings of the 2003 Symposium on VLSI Technology, (2003), pp. 9-10), it is reported that in a case where a gate-electrode material is polysilicon, the effective work function of this polysilicon is fixed at a position near the midgap (i.e., the intermediate value of band gap energy) of silicon and toward n+ polysilicon, irrespective of the type of the dopant for polysilicon and, as a result, the absolute value of the threshold voltage Vt of a pFET is considerably large. As a method for suppressing increase of the absolute value of the threshold voltage Vt resulting from the Fermi-level pinning, methods such as a method of providing a thin buffer layer made of, for example, silicon nitride (SiN) in the interface between a gate electrode and a gate insulating film and a method employing a silicate structure in the entire part of which the metal concentration is reduced as a gate insulating film have been examined. However, even these methods have a problem in which the dielectric constant of the buffer layer is lower than that of the high-κ material and the buffer layer is grown to be an island shape during deposition thereof so that the thickness needs to be large. In addition, the silicate structure having a low metal concentration causes a problem in which the effective dielectric constant of the gate insulating film is extremely reduced (i.e., the equivalent oxide thickness EOT is increased) as described above. Accordingly, each of the structure including a buffer layer and the structure with a reduced metal concentration has a trade-off relationship with the case of not adopting these structures.
Accordingly, in the case of using the high-κ material for a gate insulating film, to solve the problem of deterioration of carrier mobility in the lower interface (substrate interface) and the problem of Fermi-level pinning occurring in the upper interface (gate-electrode interface), it is necessary to provide an interface layer (an underlying film) and a buffer film such that distances are kept from the gate insulating film to the respective interfaces with the substrate and the gate electrode or to optimize the structure of the high-κ film, e.g., to reduce the metal concentration, in consideration of the trade-off of increase of the equivalent oxide thickness EOT.
For a MOSFET using a gate insulating film made of a conventional high-κ material, setting and optimization of an underlying film and a buffer film, optimization of the metal concentration in a high-κ film and change and optimization of the metal concentration profile are proposed so as to avoid deterioration of carrier mobility and occurrence of Fermi-level pinning.
However, these proposals have new problems dependent on a high-κ film deposition mechanism such as island-shape growth dependent on the underlying film as well as the buffer film and thermodynamic instability of the designed film structure.
For example, as illustrated in FIG. 11A, an underlying film 2 made of silicon oxide, a gate insulating film 3 made of metal oxide having a high dielectric constant, and a gate electrode 3 made of polysilicon are deposited in this order over a substrate 1 made of silicon so as to obtain the gate insulating film 3 having a metal concentration of about 70%, for example. However, the substrate is exposed to high-temperature processes during deposition of films and transistor formation, resulting in that the gate insulating film is separated into phases which are thermodynamically stable and have different metal concentrations, as illustrated in FIG. 11B. Specifically, the gate insulating film is three-dimensionally separated into phases: a high-κ stable phase 3a having a high dielectric constant and a low-κ stable phase 3b having a dielectric constant lower than that of the high-κ stable phase 3a, so that grain boundary is formed in the thickness direction. Along the grain boundary extending in the thickness direction, leakage current 5 flows in the substrate 1, so that the film properties of the gate insulating film 3 deteriorate.
Whether the specific phase is stable or not depends on the type of a metal element in a high-κ film. This can be estimated to some extent from, for example, the HfO2—SiO2 phase diagram in FIG. 12, the ZrO2—SiO2 phase diagram in FIG. 13 and the Y2O3—SiO2 phase diagram in FIG. 14 disclosed in non-patent literature 3 (M. Hiratani, K. Torii, and Y. Shimamoto, “Scaling Limitation of High-κ Gate Insulating Film” Semiconductor Integrated Circuit Symposium, Dec. 13 to 14 (2001), pp. 79-84), non-patent literature 4 (V. N. Parfenekov, R. G. Grebenschcikov and N. A. Torpov, Dokl. Akad. Nauk SSSR, 185[4]840 (1969)) and non-patent literature 5 (N. A. Torpov and I. A. Bonder, Izv. Akad. Nauk SSSR, Otd. Khim. Nauk 4, 547 (1961)), respectively, but depends on the thin-film effect and factors other than temperature. In FIGS. 12, 13 and 14, Liquid (L) represents a liquid phase, tet represents a tetragonal crystal layer, mon represents monoclinic phase, Trd represents tridimite phase, and Crs (Crist) represents a cristobalite phase.